JLO Management Analog

Simulate analogical, digital or mixed, linear and non-linear electronic circuits.
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JLO Management Analog Ranking & Summary

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  • Rating:
  • License:
  • Free to try
  • Price:
  • $50.00
  • Publisher Name:
  • JLO Management
  • Publisher web site:
  • http://www.sharedvt.com
  • Operating Systems:
  • Windows 7, Windows 2003, Windows Me, Windows 98, Windows 95, Windows 2000, Windows Vista, Windows XP
  • File Size:
  • 21.18MB

JLO Management Analog Tags


JLO Management Analog Description

Analog is a simulation software for analogical, digital or mixed, linear and non-linear electronic circuits. It includes a schema capture, a simulator, a module for editing results (time domain, Fourier domain) and a module for optimizing circuits. The simulator uses the symbolic computation techniques for solving the system of equations of the circuit. By principle this resolution is performed accurately, without any iteration and without any numerical round off generating errors. Its main functions are the following: Hierarchical and graphical schema capture. Analogical, linear and non-linear components. Native models of non-linear capacitors and inductors, temperature dependent resistors, magnetic core inductors and transformers with hysteresis, delay lines and filters of Butterworth, Bessel, Chebycheff and Legendre, current or voltage sources of different types, voltage or current multipliers, diodes, bipolar, JFET, MOST and MESFET transistors. Native models of gates, flip-flops, different types of digital stimulus and displays. Library of analogical and digital components. Linear, non-linear, analogical, digital and mixed simulations. Graphical results in the time domain and in the Fourier domain. Analogical and discrete Fourier transforms. Norton equivalent circuits. Transfer functions. Sensitivity calculus, Monte-Carlo simulation, worse case analysis. Parameters optimization. Context dependent help. Its main strengths are the following: Remarkable accuracy of numerical results. No convergence defects. No numerical integration defects. All circuit topologies accepted. No options to be tuned by empirical means.


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