FIR HDL Writer FIR HDL Writer is an EDA tool used to generate clear text synthesizable Verilog Register Transfer Level (RTL) code
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FIR HDL Writer Tags

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FIR HDL Writer Description

FIR HDL Writer is an EDA (Electronic Design Automation) tool that is used to generate clear text synthesizable Verilog Register Transfer Level (RTL) code to make FIR filters and testbenches. Design options include multiple channels, coefficient sets, and resource utilization specifications (for FPGAs). The designs are fully synchronous and registered to provide maximum clock frequencies. Clock rates in excess of 300Mhz have been measured on Stratix and Virtex devices (using Quartus and ISE synthesis and place and route tools). Since verification has proven itself to be time consuming task, the FIR HDL Writer creates a self checking testbench for impulse, step, and random responses, across multiple channels and coefficient sets. Since the code generated is clear text Verilog, you can migrate the design to different device families, vendors, or even to an to an Application Specific Integrated Circuit (ASIC). Take back control of your designs with clear text RTL source code! Take Back Control of Your Design Some modern FIR HDL tools have been taking away your control, limiting your options, and consuming unwanted resources. For instance, most tools which create FIR filters for FPGAs have runaway bit growth, often producing results greater than 64 bits only to be rounded at the final output down to 16 bits. Designers often face the choice of using (and paying for) extra bits in production, or writing their own filter. The FIR HDL Writer lets you limit bit width growth by allowing you to limit precision at the multiplier, as well as the final output. Clear Text RTL The FIR HDL Writer creates a clear text RTL design file, and a clear text RTL testbench. Again, most tools either use encrypted code, or create near gate level code. The generated Verilog RTL code is human readable clear text. Access to clear text RTL source puts you in charge of your code. Since the testbench and design files are clear text Verilog, RTL simulation is extremely fast. The self checking Verilog testbench provides an impulse, step, and random stimulus (across one or more channels), and checks against pre-computed ROM results. After all tests are completed, if no errors are encountered, then it displays the message ALL TESTS PASSED.

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