Hardware::Verilog::Parser A complete grammar for parsing Verilog code using Perl
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Perl module perl parser Verilog Verilog parser

Hardware::Verilog::Parser Description

A complete grammar for parsing Verilog code using Perl Hardware::Verilog::Parser is a Perl module that defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions.For example, a Hierarchy.pm uses Hardware::Verilog::Parser to overload the grammar rule for module instantiations. This single modification will print out all instance names that occur in the file being parsed. This might be useful for creating an automatic build script, or a graphical hierarchical browser of a Verilog design.This module is currently in alpha release. All code is subject to change. Bug reports are welcome.SYNOPSIS use Hardware::Verilog::Parser; $parser = new Hardware::Verilog::Parser; $parser->Filename(@ARGV); Requirements: · Perl

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